In the manufacturing of 3D chips-such as 3D NAND and FinFET devices-as well as MEMS components, one of the most formidable challenges in thin-film deposition is "step coverage."
When a substrate surface is densely packed with deep trenches and microscopic pores, deposited atoms or molecules tend to accumulate rapidly at the opening edges, leading to "premature sealing" (or "pinch-off"). This traps microscopic voids within the trenches. Such hidden voids can cause signal transmission anomalies or electrical breakdown, and may even serve as focal points for stress release during subsequent manufacturing steps.
Addressing this filling challenge is no simple task. Highly directional Physical Vapor Deposition (PVD) is largely ineffective for deep, narrow features; meanwhile, Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD)-both known for their excellent conformality-struggle when gas molecules fail to diffuse into high-aspect-ratio, narrow gaps. If not carefully managed, these processes can also significantly slow down production throughput.
The core challenge in chip manufacturing lies in precisely controlling the surface diffusion and reaction rates of precursor molecules-all while maintaining high production capacity-to ensure that deep, nanoscale-narrow gaps are filled uniformly and without any defects.